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Alif Semiconductor /AE302F40C1537LE_CM55_HP_View /DSI /DSI_PHY_IF_CFG

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Interpret as DSI_PHY_IF_CFG

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (Val_0x0)N_LANES 0PHY_STOP_WAIT_TIME

N_LANES=Val_0x0

Description

PHY Configuration Register

Fields

N_LANES

This field configures the number of active data lanes:

0 (Val_0x0): Data lane 0

1 (Val_0x1): Data lanes 0 and 1
PHY_STOP_WAIT_TIME

This field configures the minimum time PHY needs to stay in Stop state before requesting an high-speed transmission.

Links

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Register License

THIS SOFTWARE IS PROVIDED “AS IS”. NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. ALIF SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data